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TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 1 toshiba bicd integrated circuit silicon monolithic tb67 s213 ftag pwm method phase - in bipolar stepping motor driver the tb67 s213 ftag is a pwm method phase signal controlled motor driver for two - phase bipolar stepping motor. using the bicd process, th e tb67 s213 ftag is rated at 4 0v/ 2.5 a . (absolute maximum ratings) also, with the built - in vcc regulator, the tb67 s213 ftag can be o perated with a single motor power(vm) supply. features ? the tb67 s213 ftag c an operate a single bipolar stepping motor. ? pwm method current feedback control. ? operational in full, half, and quarter step resolutions. ? uses low on - resistance mosfets for output stage. ? high voltage and large current . (for specific ation, please refer to the a bsolute maximum ratings and operation ranges.) ? error detection circuits (thermal shutdown (tsd) , over current shutdown(isd), and power - on reset(por)) ? the b uilt - in vcc regulator allows the tb67 s213 ftag to operate with a single vm power supply. ? customizable pwm chopping frequency using the external components (resistance/ condenser ). ? p ackage : tb67 s213 ftag : p - wqfn36 - 0606 - 0.50 - 002 note) please be careful about thermal conditions during use. p- wqfn36 - 0606- 0.50- 002 f tag weight :0.14(g)
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 2 pin assignment * please make sure to short the corner pads and the backside exposed pad to the ground pattern of the board. (top view) 1 2 3 4 5 6 7 8 9 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 tb67 s213 ftag nc in_b2 standby gnd rs_a rs_a out_a out_a nc gnd out_a out_a gnd gnd out_b out_b gnd out_b out_b rs_b rs_b vm nc vcc nc nc nc vref_b vref_a oscm in_a1 in_a2 phase_a phase_b in_b1 gnd
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 3 block diagram * please note that in the block diagram, functional blocks or constants may be omitted or simplified for explanatory purposes . * pleas e make sure that all gnd pins are shorted to the board s ground pattern with a single point. also, make sure to take extra ca re with pattern layout, due to heat generation. please take extra care while tracing the layout of the vm, gnd and output patterns to avoid shortage across output, gnd or power supplies. if such shortage occurs, the tb67 s213 may be permanently damaged. the utmost care should also be taken for pattern designing and implementation of the tb67 s213 . if power - relevant pins such as vm, rs, out, and gnd (which is capable of running particularly large current) are wired incorrectly, an operati on error may occur or the tb67 s213 may be destroyed. the logic input pins must also be wired correctly. otherwise, the tb67 s213 may be damaged by a curr ent larger than the specified current running through the ic. step decoder (input logic) phase_a phase_b in_b1 in_b2 in_a1 in_a2 torque control 3 bit d/a (angle control) current level set vref current control vm rs _ a rs _ b vcc voltage regulator vmr detect vcc osc cr - clk converter chopper osc oscm output control ( mixed decay control ) isd/vrs tsd vmr detect output (h - bridge 2) detection circuit vm stepping motor r s comp current feedback sta ndby
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 4 pin assignment / function tb67 s213 ftag ( qfn36 ) pin no. 1 - 36 pin no. pin name function 1 in_b1 bch step resolution control 1 2 in_b2 bch step resolution control 2 3 standby standby s et pin 4 gnd ground pin 5 nc non - connection pin 6 r s _a motor ach current sense pin 7 r s _a motor ach current sense pin 8 out_a+ motor ach (+) output pin 9 out_a+ motor ach (+) output pin 10 gnd ground pin 11 out_a motor ach ( - ) output pin 12 out_a motor ach ( - ) output pin 13 gnd ground pin 14 nc non - connection pin 15 gnd ground pin 16 out_b motor bch ( - ) output pin 17 out_b motor bch ( - ) output pin 18 gnd ground pin 19 out_b motor bch (+) output pin 20 out_b motor bch (+) output pin 21 r s _b motor bch current sense pin 22 r s _b motor bch current sense pin 23 vm vm power supply pin 24 nc non - connection pin 25 vcc internal vcc regulator monitor pin 26 nc non - connection pin 27 nc non - connection pin 28 nc non - connection pin 29 gnd gr ound pin 30 v ref _b motor bch current threshold set pin 31 v ref _a motor ach current threshold set pin 32 oscm internal oscillator frequency set pin 33 in_a1 ach step resolution control 1 34 in_a2 ach step resolution control 2 35 phase_a ach phase set pin 36 phase_b bch phase set pin ? please do not run patterns under nc pins. ? please short the pins with the same pin names, while using the tb67 s213.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 5 equivalent circuit tb67 s213 ftag ( qfn36 ) the e quivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. pin no pin name 1 in_b1 2 in_b2 3 standby 6,7 r s _a 8,9 out_a+ 11,12 out_a 16,17 out_b 19,20 out_b 21,22 r s _b 23 vm 25 vcc 30 v ref _b 31 v ref _a 32 oscm 33 in_a1 34 in_ a2 35 phase_a 36 phase_ b 100k 1 k 1,2,3,33,34, 35,36 6,7 21,22 8,9 19,20 1 1,12 16,17 500 1k 32 30,31 1k 25 gnd gnd gnd gnd
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 6 function explanation stepping motor control note: the current is defined + (plus) when the motor current flows from out_x+ - > out_x -. also, the current is defined - (minus) when the motor current flows from out_x - - > out_x+. phase a phase b input output input output phase_a in_a1 in_a2 iout(a) phase_b in_b1 in_b2 iout(b) h h h 100% h h h 100% l h h -100% h h h 100% l h h -100% l h h -100% h h h 100% l h h -100% in_a1,in_a2,in_b1,in_b2 is recommended to set to low level during power - on sequence. < half step resolution > phase a phase b input output input output phase_a in_a1 in_a2 iout(a) phase_b in_b1 in_b2 iout(b) h h h 100% h h h 100% x l l 0% h h h 100% l h h -100% h h h 100% l h h -100% x l l 0% l h h -100% l h h -100% x l l 0% l h h -100% h h h 100% l h h -100% h h h 100% x l l 0% x : don't care
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 7 < quarter step resolution > phase a phase b input output input output phase_a in_a1 in_a2 iout(a) phase_b in_b1 in_b2 iout(b) h h l 71% h h l 71% h l h 38% h h h 100% x l l 0% h h h 100% l l h -38% h h h 100% l h l -71% h h l 71% l h h -100% h l h 38% l h h -100% x l l 0% l h h -100% l l h -38% l h l -71% l h l -71% l l h -38% l h h -100% x l l 0% l h h -100% h l h 38% l h h -100% h h l 71% l h l -71% h h h 100% l l h -38% h h h 100% x l l 0% h h h 100% h l h 38% x : don't care o ther functions pin name h l notes phase _ x o ut_x h out_x l o ut_x l out_x h when set to h , the motor current is set to flow from out_x+ - > out_x -. standby motor function ready standby mode when the standby pin is set to low , the internal osc and motor output stage will be set to off status; therefore the motor will not be operational.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 8 absolute maximum ratings (ta = 25 c) characteristics symbol rating unit note motor power supply vm 40 v - motor output voltage vout 40 v - motor output current iout 2.5 a note 1 vcc voltage vcc 6.0 v - digital input voltage vin(h) 6.0 v - vin(l) - 0.4 v - power dissipation qfn 36 pd 1.15 w note 2 operating temperature topr -20 to 85 - storage temperature tstr -55 to 150 - junction temperature tj(max) 150 - note 1: while in use, please make sure that the motor current is control led to be under 80 % of the absolute maximum ratings. (in this case, about 2.0a (max) ). note 2: the value in the state where it is not mounted on the board ta : ambient temperature . topr : operating a mbient temperature . tj : operating j unction temperature. the maximum junction temperature is limited by the thermal shutdown. note : use the maximum junction temperature (tj) at 120c or less. the m aximum current cannot be used under certain thermal conditions. note : the absolute maximum ratings the absolute maximum ratings are a specification that must not be exceeded, even for a moment. exceeding the ratings may cause device breakdown, damage or deterioration, and may result in injury by e xplosion or combustion . operating ranges (ta=0 to 85) characterist ics symbol min typ max unit note motor power supply vm 10 24 35 v motor output current iout - 1. 0 2.0 a logic input voltage vin(h) 2.0 - 5. 5 v l ogic high level vin(l) 0 - 0.8 v l ogic low level clk input frequency f clk - - 100 khz pwm signal f requency range fchop(range) 40 100 150 khz vref reference voltage vref gnd 3.0 3.6 v rs pin voltage vrs - 1.0 1.5 v reference value: vm note 1: the actual maximum current may be limited by the operating environment (operating conditions such as e xcitation mode or operating duration, or by the surrounding temperature or board heat dissipation). determine a realistic maximum curre nt by calculating the heat generated under the operating environment. note 2: the maximum vrs voltage should not exceed t he maximum rated voltage.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 9 electrical specifications 1 (ta=25 , vm=24v, unless specified otherwise) characteristics symbol test circuit test condition min typ. max unit logic input pin voltage high vin(h) dc logic input pins (note) 2 - 5.5 v low vin(l) dc logic input pins (note) 0 - 0.8 v logic input voltage hy sterisis vin(hys) dc logic input pins (note) 100 - 300 mv logic input pin current high iin(h) dc logic input pins; vin=3.3v - 33 50 a low iin(l) dc logic input pins; vin=0v - - 1 a power consumption im1 dc output:open, standby mode - 2 3 ma im2 dc output:open, enable=l - 3.5 5 ma im3 dc output:open (full step setting) - 5 7 ma motor output leakage current hi - side ioh dc vrs=vm=40v,vout=0v - - 1 a low - side iol dc vrs=vm=vout=40v 1 - - a bridge - to - bridge current differential iout1 dc channel a and b differential -5 0 5 % output current error relative to the predetermined value iout2 dc iout=1.0a -5 0 5 % rs pin current irs dc vrs = vm =24v 0 - 10 a drain - source on- resistance (the sum of high side & low side) ron(s)_pn iout=2.0a, tj=25 , ( hi - side+low side mosfet) 0 .53 0 .75 note: v in (l h) is defined as the v in voltage that causes the outputs ( out_a + , out_a - , out_b + and out_b - ) to change when a pin under test is gradually raised from 0 v. v in (h l) is defined as the v in voltage t hat causes the outputs ( out_a +, out_a - , out_b + and out_b - ) to change when th e pin is then gradually lowered. the difference between v in (l h) and v in (h l) is defined as the input hysteresis. note: the internal circuits are designed to avoid miss -fu nction or leakage current; when the logic signal is applied while the vm voltage is not supplied. but for fail - safe, please control the power supply and ogic signal timing correctly.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 10 electrical specifications 2 (ta=25 , vm=24v, unless specified otherwise) characteristics symbol test circuit test condition min typ. max unit vref input voltage vref dc vm=24v,vcc=5v gnd 3.0 3.6 v vref input current iref vref =3.0v - 0 1 a vcc voltage vcc icc=5.0ma 4.75 5.0 5.25 v vcc curre nt icc vcc=5.0v - 2.5 5 ma vref gain vref(gain) vref =2.0v 1/ 5.2 1/5.0 1/ 4.8 tsd threshold (note1) t j tsd 140 150 170 vm por threshold vmr 7.0 8.0 9.0 v over current threshold (note2) isd (3. 1) (4. 0) (5. 0) a note 1: thermal shutdown (tsd ) circuit wh en the junction temperature of the device reaches the tsd threshold, the tsd circuit is triggered; the internal reset circuit then turns off the output transistors. once the tsd circuit is triggered, the device keeps the output off until power - on reset (por), is reasserted or set to standby mode . note 2: over - current/voltage shutdown (isd) circuit w hen the output current or the rs pin voltage reaches the threshold, the isd circuit is triggered; the internal reset circuit then turns off the out put transistors. once the isd circuit is triggered, the device keeps the output off until power - on reset (por), is reasserted or set to standby mode . for fail - safe, please insert a fuse to avoid secondary trouble. back - emf while a motor is rotating, the re is a timing at which power is fed back to the power supply. at that timing, the motor current recirculates back to the power supply due to the effect of the motor back - emf. if the power supply does not have enough sink capability, the power supply and o utput pins of the device might rise above the rated voltages. the magnitude of the motor back - emf varies with usage conditions and motor characteristics. it must be fully verified that there is no risk that the tb 67 s213 or other components will be damaged or fail due to the motor back - emf. cautions on overcurrent shutdown (isd) and thermal shutdown (tsd) ? the isd and tsd circuits are only intended to provide temporary protection against irregular conditions such as an output short - circuit; they do not neces sarily guarantee the complete ic safety. ? if the device is used beyond the specified operating ranges, these circuits may not operate properly: then the device may be damaged due to an output short - circuit. ? the isd circuit is only intended to provide a temp orary protection against an output short - circuit. if such a condition persists for a long time, the device may be damaged due to overstress. overcurrent conditions must be removed immediately by external hardware. ic mounting do not insert devices incorre ctly or in the wrong orientation. otherwise, it may cause breakdown, damage and/or deterioration of the device.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 11 electrical specifications 2 (ta = 25 c, vm = 24 v, 6.8 mh/5.7 ) characteristics symbol test circuit test condition min typ. max uni t phase inpu t frequency f phase ac fosc =1600khz - - 150 khz minimum phase high width t phase (h) ac minimum phase width: phase =h 50 - - ns minimum phase low width tphase (l) ac minimum phase width: phase =l 50 - - ns output stage s witching specification s tr ac 150 200 250 ns tf ac 100 150 200 ns tplh (clk) ac phase to out 250 - 1200 ns tphl (clk) ac phase to out 250 - 1200 ns analog noise rejection blank time atblk ac vm=24v,iout=1.0a analog tblk 250 400 550 ns internal oscillator frequency fosc ac cosc = 270 pf, rosc =3.6 k 1360 1600 1840 khz motor chopping frequency fchop ac output active ( iout = 1.0 a) , fosc = 1600 khz - 100 - khz ac timing chart timing charts may be simplified for explanatory purpose. tphase (h) t phase (l) tplh( phase ) tphl( phase ) 10% 90% tr 90% 10% tf phase out 50% 50% 50% 50% 50% fphase
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 12 application note motor control (current feedback control) the mixed decay timing is a fixed value of 37.5% of 1 fchop cycle. waveform of mixed decay mode sequence (motor current) timing charts may be simplified for explanatory purposes. note: about mixed decay timing mixed decay timing ( mdt ) is a unique value of th e tb 67 s213 ( fchop 37.5% ), but when the motor output current reaches nf threshold after mdt, the rest of fchop ( ) becomes fast decay mode. n f detect fcho p 37.5% m ixed d ecay m ode osc internal waveform mdt (m ixed d ecay t iming ): 37.5% fchop f chop 1cycle 16clk 6 clk / 16clk = 37.5% fchop c harge m ode o nf detect o s low m ode o m ixed d ecay timing o f ast m ode o c harge mod e iout current threshold mdt n f detect nf detect c urrent threshold 37.5% m ixed d ecay m ode osc internal waveform iout fchop fchop
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 13 mixed (slow + fast) decay mode current waveform ? when the next step s current threshold is above the preious st ep ? when the next step s current threshold is below the preious step timing charts may be simpl ified for explanatory purposes. slow slow slow slow f ast f ast charge cha rge f ast charge fast charge current threshold nf nf nf nf slow f ast charge slow f ast charge current threshold f ast slow f ast slow nf nf charge nf charge nf nf charge an instant c harge mode will enable the driver to compare the motor cu rrent and the current threshold. f chop f chop f chop f chop current threshold osc internal waveform fchop fchop fchop fchop current threshold osc internal waveform
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 14 output transistor operation mode some of the functional blocks, circuits, or constants omitted or simplified for explanatory purpose. output transistor operational function mode u1 l1 u2 l2 charge on off off on slow decay off on off on fast decay off on on off no te: the parameters shown in the table above are examples when the current flows in the directions shown in the figures above. for the current flowing in the reverse direction, the parameters change as shown in the table below. mode u1 l1 u2 l2 charge o ff on on off slow decay off on off on fast decay on off off on u1 l1 u2 l2 gnd u1 l1 u2 l2 u1 l1 u2 l2 rs rrs vm charge slow decay fast decay rs rrs vm rs rrs vm gnd gnd on on on on on on
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 15 calculation of the predefined output current for pwm constant - current control, the tb67 s213 ft a g uses a clock generated by the cr oscillator. the peak output current can be set via th e current - sensing resistor (rrs) and the reference voltage (vref), as follows: iout = vref/5 rrs () where, 1/5 is the vref decay rate, vref (gain). for the value of vref (gain), see the electrical characteristics table.for example, when vref = 3 v, t o set the current feedback threshold (iout)=1.8a, rs resistance is calculated as: rrs = (vref /5) iout = (3/5) 1.8 = 0.33. ( 1.1 w) calculation of the oscm oscillation frequency (chopper reference frequency) an approximation of the oscm oscillat ion frequency (foscm) and chopper frequency (fchop) can be calculated by the following expressions. foscm=1/[0. 56 x{cx(r1+500)}] c,r1: external co mponents for oscm (c=270pf , r=3.6k? => 1.6mhz ) fchop = foscm / 16 ic power consumption the power consumed by the tb6 7 s213 ft a g is approximately the sum of the following: 1) the power consumed by the output transistors 2) the power consumed by the digital logic and pre - drivers. the power consumed by the output transistors is calculated, using the ron (d - s) value of 0.6 (typ) . an approximation of the peak power consumption for h - sw can be calculated by the following expressions. p (out) = h - sw(ch ) iout (a) iout (a) ron ( ) (1) in full step operation (for example, 1.0a), the average power consumption in the output stage is calculated as follows: ron = 0. 6 , iout = 1. 0 a, vm = 24 v p (out) = 2 ( ch ) 1. 0 (a) ^ 2 0. 6( ) (2) = 1. 2 (w) the power consumption in the im domain is calculated as : p (im) = 24 (v) 0.005 (a) (3) = 0.12 (w) (im3) 5.0 ma (typ.) , vm=24v all over, the total peak power consumption of tb6 7 s213 ftag is: p = p (out) + p (im) = 1. 32 (w) board design should be fully verified, taking thermal dissipation into consideration.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 16 step resolution timing char ts ( phase - in) [full step resolution] timing charts may be simplified for explanator y purposes. phase_a phase_b i out (a) in_a1 in_a2 in_b1 in_b2 0% 100% -100% 0% -100% 100% h l h l h l h l h l h l
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 17 [half step resolution] timing charts may be simplified for explanatory purposes. phase_a i out (a) i out (b) in_a1 in_a2 phase_b in_b1 in_b2 0% 100% -100% 0% -100% 100% h l h l h l h l h l h l
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 18 [quarter step resolution] timing charts may be simplifie d for explanatory purposes. phase_a i out _a i out _b in_a1 in_a2 phase_b in_b1 in_b2 0% 38% 71% 100% - 38% - 71% - 100% 0% 38% 71% - 38% - 71% - 100% 100% h l h l h l h l h l h l
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 19 gnd 24v 0.1f 0. 22 ? 0.1f 100f m 0. 22 ? 3.6k? 270pf 0.1f gnd oscm in_b1 vref _b phase_a in_a2 phase_b vref _a in_b2 r s _a r s _a out_a + out_a + gnd gnd gnd out_b - out_b - gnd out_a - gnd out_a - vm v cc r s _b r s _b out_b + out_b + stand by 0v 5v 3.3v 0v 5v 3.3v 0v 5v 3.3v 0v 5v 3.3v 0v 5v 3.3v 0v 5v 3.3v 0v 5v 3.3v in_a1 example application circuit s the values shown in the following figure are typical values. for input conditions, see the operating ranges. note: bypass capacitors shou ld be added as necessary. it is recommended to use a single ground plane for the entire board whenever possible. the above application circuit example is presented only as a guide and should be fully evaluated prior to production. also, no intellectual pr operty right is ceded in any way whatsoever in regard to its use.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 20 package dimensions p- wqfn36 - 0606- 0.50- 002 unit:mm
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 21 notes on contents block diagrams some of the functional blocks, circuits, or constants in the bl ock diagram may be omitted or simplified for explanatory purposes. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. timing charts timing charts may be simplified for exp lanatory purposes. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required at the mass production design stage. toshiba does not grant any license to any industrial pro perty rights by providing these examples of application circuits. test circuits components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or fail ure from occurring in the application equipment. ic usage considerations notes on handling of ics the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result in injury by explosion or combustion. use an appropriate power supply fuse to ensure that a large current does not continuously flow in the case of over - current an d/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead to smoke or ignition. to minimize the effects of the flow of a large current in the case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. if your design i ncludes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resultin g from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built - in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic br eakdown may cause injury, smoke or ignition. do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may excee d the absolute maximum rating, and exceeding the rating(s) may cause device breakdown, damage or deterioration, and may result in injury by explosion or combustion. in addition, do not use any device that has been insert ed incorrectly. please take extra c are when selecting external components (such as power amps and regulators) or external devices (for instance, speakers). when large amount s of leak current occurs from capacitors , the dc output level may increase. if the output is connected to devices such as speaker s with low resist voltage, overcurrent or ic failure may cause smoke or ignition. (the over - current may cause smoke or ignition from the ic itself.) in particular, please pay attention when using a bridge tied load (btl) connection - type ic that inputs output dc voltage to a speaker directly.
TB67S213FTAG 2013 - 0 8 - 19 ver. 1 .0 2 22 points to remember on handling of ics over current detection c ircuit over current detection circuits (referred to as current limiter circuits) do not necessarily protect ics under all circumstances. if the over current detection circuits operate against the over current, clear the over current status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over current protection circui t to not operate properly or ic breakdown before operation. in addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the ic may generate heat resulting in breakdown. thermal shutd own circuit thermal shutdown circuits do not necessarily protect ics under all circumstances. if the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. depending on the method of use and usage cond itions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or ic breakdown before operation. heat radiation design in using an ic with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (tj) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic li fe, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. back - emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motors power supply due to the effect of back - emf. if the current sink capability of the power supply is small, the devices motor power supply and output pins might be exposed to conditions beyond maximum ratings. to avoid this problem, take the effect of back - emf into consideration in system design.
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do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). product and related software and technology may be controlled under the applicable expor t law s and regulations including, without limitation, the japanese foreign exchange and foreign trade law and the u.s. export admini stration regulations. export and re - export of product or related software or technology are strictly prohibited except in complia nce with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pr oduct. please use product in compliance with all applicable laws and regulat ions that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losse s occurring as a result of nonco mpliance with applic able laws and regula tions.

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